One aspect of the present disclosure relates to a modular single-chip dual-band MIMO transceiver. The modular design approach disclosed herein provides a scalable (N×N) dual-band MIMO transceiver suitable for IEEE 802.11n WLAN applications. Another aspect of the present invention relates to generating oscillating signals in wireless electronic circuits and to dividing such signals, and in particular, to injection-locking frequency divider circuits and methods that may be used in a wireless system.
The demand for high speed wireless networking is rapidly increasing. High speed wireless networks are desired for both enterprise and consumer applications. As high speed wireless networks evolve and become more ubiquitous, there is a constant demand for higher throughput and longer range.
IEEE 802.11n is a wireless networking standard that addresses these needs. IEEE 802.11n employs multiple-input multiple-output (MIMO) transceiver technology to improve performance. MIMO transceivers allow multiple independent spatial data streams to be transmitted or received simultaneously over the same spectral channel of bandwidth. Within a MIMO transceiver each data stream requires a discrete antenna and its own RF processing chain. In order to achieve low costs, low power consumption and a small form factor, an integrated multi-transceiver approach is desired. A unique feature of IEEE 802.11n is that it allows great flexibility in the number and configuration of the spatial data streams in order to meet various system requirements.
Typical MIMO transceivers include a local oscillator for generating a local oscillator signal which is distributed to transceiver blocks located elsewhere on an integrated circuit chip. In order to reduce the form factor of the MIMO transceiver chip, the transceiver blocks are typically arranged adjacent to or as near as possible to the local oscillator. For example, a 2T×2R MIMO transceiver may include a pair of transceiver blocks symmetrically placed on either side of the local oscillator so that the local oscillator signal may be conveniently provided to both transceiver blocks. MIMO transceivers with a greater number of spatial channels, such as 3T×3R or 4T×4R MIMO transceivers, may have transceiver blocks arranged in a more circular or semi-circular pattern around the local oscillator in order to receive the local oscillator signal directly from the local oscillator.
A problem with the existing design approach is that it is not easily scalable. Significant design changes are required to the chip floor plan if it is desired to add an additional spatial channel or otherwise alter the configuration or capacity of the MIMO transceiver. Additionally, the irregular placement of the transceiver blocks in current MIMO transceiver designs make path matching for the separate spatial channels difficult. What is more, each additional transceiver block requires at least 4 additional pins for interfacing the transmit (Tx) and receive (Rx) signals between the transceiver chip and the baseband circuitry of the WLAN system in which the MIMO transceiver is installed. The additional pins for larger MIMO transceivers further complicate the design requirements of a single chip MIMO transceiver.
A new scalable design approach toward single chip MIMO transceivers is desired. Such a new design approach should allow MIMO transceivers of substantially any size to be produced without significant redesign requirements. Such a design approach should also provide adequate path matching between Tx and Rx signal path and provide adequate separation between Tx ports of the same frequency. An improved MIMO transceiver should also reduce the number of pins required to interface the transceiver with the WLAN baseband circuitry.
Mobile communication devices and the evolution of the internet have increased the demand on wireless communication bandwidth. Multiple-input multiple-output (MIMO) is one example technology which is used to sustain a higher data bandwidth. MIMO, like other technologies, require synthesis and processing of high frequency signals such as, for example, local oscillator (“LO”) signals that may be used to up-convert or down-convert a carrier frequency. Frequency dividers may be utilized to create additional signals having different frequencies to facilitate this process.
FIG. 1A illustrates a prior art frequency divider 100 used to create an oscillating signal. Frequency divider 100 includes series connected D-flip flops 101 and 102. A clock input 103 provides an input to frequency divider 100. Frequency divider 100 utilizes input 103 to produce Vout at one-half the frequency of input 103.
FIG. 1B illustrates an input waveform 104 and an output waveform 105 corresponding to the prior art frequency divider 100 of FIG. 1A. Input waveform 104 corresponds to the input clock 103 of FIG. 1A. Output waveform 105 corresponds to Vout of FIG. 1A. Period T2 is twice as long as T1, and therefore, the frequency of output waveform 105 is one-half the frequency of input waveform 104.
FIG. 1C illustrates example circuit 120 using source coupled logic (SCL) to implement a D-flip flop in a frequency divider. Frequency divider 120 is useful in some applications, but has some major disadvantages. For example, frequency divider 120 has a high power consumption, has a limited output swing, does not drive capacitive loads well, and may have an asymmetric output waveform. The high power consumption creates a problem with battery life in mobile wireless solutions. The limited output swing may limit the implementation in low voltage technologies. Additionally, the circuit may require additional buffering to improve capacitive drive capability. The asymmetric output waveform may introduce unwanted additional frequencies which may interfere with the transmitter and receive channels of the system.
FIG. 1D illustrates a prior art injection-locking frequency divider 140. An injection current Iinj 147 is a current signal having a frequency component which is used to create Vout 149. The output frequency of Vout 149 may be one-half the frequency of Iinj 147. While this implementation is also useful in some applications, it also has several disadvantages. For example, the injection current in frequency divider 140 may be highly sensitive to interference from other signals on the same integrated circuit. In particular, power amplifiers (PAs) from other portions of an integrated chip may contribute signals into the ground plane of the integrated circuit. These signals may interfere with Iinj 147 and cause the circuit to lock to the wrong frequency. This phenomenon is sometimes referred to as injection pulling caused by a power amplifier or other circuit and may be particularly problematic on integrated circuits with multiple power amplifiers such as a MIMO system. Additionally, frequency divider 140 may also be susceptible to common mode problems. In particular, frequency divider 140 may develop a common mode output at the same frequency as the injection signal.
Thus, there is a need for improved techniques for generating oscillating signals in a wireless communication system, and in particular, to improved frequency divider circuits that may be used in such applications.